﻿/*
 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * Description: efuse driver header file.
 * Create: 2020-01-01
 */

#ifndef __EFUSE_OPT_H__
#define __EFUSE_OPT_H__

#include "osal_types.h"

#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif

#define EFUSE_TIMER0_12US 0x120
#define EFUSE_DELAY_TIMES 500000
#define WRITE_EN 0xa5a5
#define READ_EN 0x5a5a

#define RETRY_TIMES                         10000
#define EFUSE_DELAY_1_US                    1

#define EFUSE_USB_SDIO_PID_BIT              944
#define EFUSE_USB_SDIO_PID_BIT_LEN          16
#define EFUSE_USB_SDIO_VID_BIT              960
#define EFUSE_USB_SDIO_VID_BIT_LEN          16
#define EFUSE_READ_BIT_LEN                  8
#define EFUSE_PID_1_OFFSET                  8
#define EFUSE_VID_0_OFFSET                  16
#define EFUSE_VID_1_OFFSET                  24
#define EFUSE_ID_MASK                       0xff
#define BIT_TO_BYTE                         3

#define EFUSE_DIEID_BIT_BEGIN              8
#define EFUSE_DIEID_BIT_SN_LEN             96
#define EFUSE_DIEID_BYTE_SN_LEN            (EFUSE_DIEID_BIT_SN_LEN >> 3)

#define EFUSE_USB_CTRL_BEGIN            368
#define EFUSE_CTRL_PWR_LEN              5
#define EFUSE_CTRL_PHY_TRIM             53

#define EFUSE_MAX_INDEX  1023
#define EFUSE_MAX_READ_BIT 8
#define SIZE_8_BITS 8
#define MAX_OFFSET_COMP 7
#define THREE_BITS_OFFSET 3

#define MAC_ADDR_0_EFUSE_START_BIT 800
#define MAC_ADDR_1_EFUSE_START_BIT 848
#define MAC_ADDR_2_EFUSE_START_BIT 896
#define PID_EFUSE_START_BIT 944
#define VID_EFUSE_START_BIT 960

#define EFUSE_MAC_NUM 3
#define EFUSE_VID_PID_SIZE 16

#define EFUSE_LOCK_START_BITS         976    /* 第一加锁区起始bit */
#define HELP_LEN 7

typedef enum {
    EXT_EFUSE_CHIP_ID = 0,
    EXT_EFUSE_DIE_ID = 1,
    EXT_EFUSE_R_CAL_ID = 2,
    EXT_EFUSE_RC_CAL_ID = 3,
    EXT_EFUSE_TYPE_ID = 4,
    EXT_EFUSE_POC_CTRL_ID = 5,
    EXT_EFUSE_RC_32K_LP_RES_TRIM_ID = 6,
    EXT_EFUSE_PMU_REF_BG_TRIM1_ID = 7,
    EXT_EFUSE_PMU_REF_BG_TRIM2_ID = 8,
    EXT_EFUSE_XLDO_TRIM_ID = 9,
    EXT_EFUSE_PLLLDO_1P0_TRIM_ID = 10,
    EXT_EFUSE_ABBLDO_1P0_TRIM_ID = 11,
    EXT_EFUSE_VCOLDO_1P0_TRIM_ID = 12,
    EXT_EFUSE_INALDO_1P0_TRIM_ID = 13,
    EXT_EFUSE_RXLDO_1P0_TRIM_ID = 14,
    EXT_EFUSE_TXLDO_1P8_TRIM_ID = 15,
    EXT_EFUSE_TXLDO_1P0_TRIM_ID = 16,
    EXT_EFUSE_CMULDO0_0P9_TRIM_ID = 17,
    EXT_EFUSE_CMULDO1_0P9_TRIM_ID = 18,
    EXT_EFUSE_CMULDO_1P8_TRIM_ID = 19,
    EXT_EFUSE_INTLDO_TRIM_ID = 20,
    EXT_EFUSE_PHYLDO_TRIM_ID = 21,
    EXT_EFUSE_CMU_XO_TRIM_COARSE_ID = 22,
    EXT_EFUSE_CMU_XO_TRIM_FINE_ID = 23,
    EXT_EFUSE_CMU_RESERVED_ID = 24,
    EXT_EFUSE_JTM_ID = 25,
    EXT_EFUSE_SSI_SPI_MASK_ID = 26,
    EXT_EFUSE_WIFI6_SW_ID = 27,
    EXT_EFUSE_SLE_SW_ID = 28,
    EXT_EFUSE_XO_PPM_TEMPERATURE_1_ID = 29,
    EXT_EFUSE_XO_PPM_TEMPERATURE_2_ID = 30,
    EXT_EFUSE_DIED_ID_RVSD_ID = 31,
    EXT_EFUSE_WIFI_IPA_I_CAL_ID = 32,
    EXT_EFUSE_BT_IPA_I_CAL_ID = 33,
    EXT_EFUSE_TX_CAL_FB_GAIN_H_ID = 34,
    EXT_EFUSE_TX_CAL_FB_GAIN_L_ID = 35,
    EXT_EFUSE_RX_GAIN_ID = 36,
    EXT_EFUSE_RF_GAIN_ID = 37,
    EXT_EFUSE_CHIP_RSVD1_ID = 38,
    EXT_EFUSE_USB2_PHY_TRIM_ID = 39,
    EXT_EFUSE_USB_SDIO_VID_ID = 40,
    EXT_EFUSE_USB_CTRL_PWR_ID = 41,
    EXT_EFUSE_REDUNDANCY_ID = 42,
    EXT_EFUSE_CHIP_SECURE_BOOT_ID = 43,
    EXT_EFUSE_CHIP_RSVD_ID = 44,
    EXT_EFUSE_CUSTOMER_RSVD_ID = 45,
    EXT_EFUSE_XO_PPM_1_ID = 46,
    EXT_EFUSE_CURV_FACTOR_HIGN_1_ID = 47,
    EXT_EFUSE_CURV_FACTOR_LOW_1_ID = 48,
    EXT_EFUSE_11B_HIGN_1_ID = 49,
    EXT_EFUSE_11B_LOW_1_ID = 50,
    EXT_EFUSE_OFDM_20M_HIGN_1_ID = 51,
    EXT_EFUSE_OFDM_20M_LOW_1_ID = 52,
    EXT_EFUSE_OFDM_40M_HIGN_1_ID = 53,
    EXT_EFUSE_OFDM_40M_LOW_1_ID = 54,
    EXT_EFUSE_RSSI_BAND1_1_ID = 55,
    EXT_EFUSE_RSSI_BAND2_1_ID = 56,
    EXT_EFUSE_RSSI_BAND3_1_ID = 57,
    EXT_EFUSE_GROUP_USED_FLAG1_ID = 58,
    EXT_EFUSE_XO_PPM_2_ID = 59,
    EXT_EFUSE_CURV_FACTOR_HIGN_2_ID = 60,
    EXT_EFUSE_CURV_FACTOR_LOW_2_ID = 61,
    EXT_EFUSE_11B_HIGN_2_ID = 62,
    EXT_EFUSE_11B_LOW_2_ID = 63,
    EXT_EFUSE_OFDM_20M_HIGN_2_ID = 64,
    EXT_EFUSE_OFDM_20M_LOW_2_ID = 65,
    EXT_EFUSE_OFDM_40M_HIGN_2_ID = 66,
    EXT_EFUSE_OFDM_40M_LOW_2_ID = 67,
    EXT_EFUSE_RSSI_BAND1_2_ID = 68,
    EXT_EFUSE_RSSI_BAND2_2_ID = 69,
    EXT_EFUSE_RSSI_BAND3_2_ID = 70,
    EXT_EFUSE_GROUP_USED_FLAG2_ID = 71,
    EXT_EFUSE_IPV4_MAC_ADDR_01_ID = 72,
    EXT_EFUSE_IPV4_MAC_ADDR_02_ID = 73,
    EXT_EFUSE_IPV4_MAC_ADDR_03_ID = 74,
    EXT_EFUSE_USB_SDIO_PID_ID = 75,
    EXT_EFUSE_USB_SDIO1_VID_ID = 76,
    EXT_EFUSE_LOCK_CHIP_ID = 77,
    EXT_EFUSE_LOCK_DIE_ID = 78,
    EXT_EFUSE_LOCK_R_CAL_ID = 78,
    EXT_EFUSE_LOCK_RC_CAL_ID = 78,
    EXT_EFUSE_LOCK_TYPE_ID = 79,
    EXT_EFUSE_LOCK_POC_CTRL_ID = 80,
    EXT_EFUSE_LOCK_RC_32K_LP_RES_TRIM_ID = 81,
    EXT_EFUSE_LOCK_PMU_REF_BG_TRIM1_ID = 81,
    EXT_EFUSE_LOCK_PMU_REF_BG_TRIM2_ID = 81,
    EXT_EFUSE_LOCK_XLDO_TRIM_ID = 81,
    EXT_EFUSE_LOCK_PLLLDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_ABBLDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_VCOLDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_INALDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_RXLDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_TXLDO_1P8_TRIM_ID = 81,
    EXT_EFUSE_LOCK_TXLDO_1P0_TRIM_ID = 81,
    EXT_EFUSE_LOCK_CMULDO0_0P9_TRIM_ID = 81,
    EXT_EFUSE_LOCK_CMULDO1_0P9_TRIM_ID = 81,
    EXT_EFUSE_LOCK_CMULDO_1P8_TRIM_ID = 81,
    EXT_EFUSE_LOCK_INTLDO_TRIM_ID = 81,
    EXT_EFUSE_LOCK_PHYLDO_TRIM_ID = 81,
    EXT_EFUSE_LOCK_CMU_XO_TRIM_COARSE_ID = 82,
    EXT_EFUSE_LOCK_CMU_XO_TRIM_FINE_ID = 82,
    EXT_EFUSE_LOCK_CMU_RESERVED_ID = 82,
    EXT_EFUSE_LOCK_JTM_ID = 83,
    EXT_EFUSE_LOCK_SSI_SPI_MASK_ID = 84,
    EXT_EFUSE_LOCK_WIFI6_SW_ID = 85,
    EXT_EFUSE_LOCK_SLE_SW_ID = 86,
    EXT_EFUSE_LOCK_XO_PPM_TEMPERATURE_1_ID = 87,
    EXT_EFUSE_LOCK_XO_PPM_TEMPERATURE_2_ID = 87,
    EXT_EFUSE_LOCK_DIED_ID_RVSD_ID = 87,
    EXT_EFUSE_LOCK_WIFI_IPA_I_CAL_ID = 88,
    EXT_EFUSE_LOCK_BT_IPA_I_CAL_ID = 89,
    EXT_EFUSE_LOCK_TX_CAL_FB_GAIN_H_ID = 90,
    EXT_EFUSE_LOCK_TX_CAL_FB_GAIN_L_ID = 90,
    EXT_EFUSE_LOCK_RX_GAIN_ID = 90,
    EXT_EFUSE_LOCK_RF_GAIN_ID = 91,
    EXT_EFUSE_LOCK_CHIP_RSVD1_ID = 92,
    EXT_EFUSE_LOCK_USB2_PHY_TRIM_ID = 93,
    EXT_EFUSE_LOCK_USB_SDIO_VID_ID = 94,
    EXT_EFUSE_LOCK_USB_CTRL_PWR_ID = 94,
    EXT_EFUSE_LOCK_REDUNDANCY_ID = 94,
    EXT_EFUSE_LOCK_CHIP_SECURE_BOOT_ID = 95,
    EXT_EFUSE_LOCK_CHIP_RSVD_ID = 95,
    EXT_EFUSE_LOCK_CUSTOMER_RSVD_ID = 96,
    EXT_EFUSE_LOCK_XO_PPM_1_ID = 97,
    EXT_EFUSE_LOCK_CURV_FACTOR_HIGN_1_ID = 98,
    EXT_EFUSE_LOCK_CURV_FACTOR_LOW_1_ID = 99,
    EXT_EFUSE_LOCK_11B_HIGN_1_ID = 100,
    EXT_EFUSE_LOCK_11B_LOW_1_ID = 101,
    EXT_EFUSE_LOCK_OFDM_20M_HIGN_1_ID = 102,
    EXT_EFUSE_LOCK_OFDM_20M_LOW_1_ID = 103,
    EXT_EFUSE_LOCK_OFDM_40M_HIGN_1_ID = 104,
    EXT_EFUSE_LOCK_OFDM_40M_LOW_1_ID = 105,
    EXT_EFUSE_LOCK_RSSI_BAND1_1_ID = 106,
    EXT_EFUSE_LOCK_RSSI_BAND2_1_ID = 107,
    EXT_EFUSE_LOCK_RSSI_BAND3_1_ID = 108,
    EXT_EFUSE_LOCK_XO_PPM_2_ID = 109,
    EXT_EFUSE_LOCK_CURV_FACTOR_HIGN_2_ID = 110,
    EXT_EFUSE_LOCK_CURV_FACTOR_LOW_2_ID = 111,
    EXT_EFUSE_LOCK_11B_HIGN_2_ID = 112,
    EXT_EFUSE_LOCK_11B_LOW_2_ID = 113,
    EXT_EFUSE_LOCK_OFDM_20M_HIGN_2_ID = 114,
    EXT_EFUSE_LOCK_OFDM_20M_LOW_2_ID = 115,
    EXT_EFUSE_LOCK_OFDM_40M_HIGN_2_ID = 116,
    EXT_EFUSE_LOCK_OFDM_40M_LOW_2_ID = 117,
    EXT_EFUSE_LOCK_RSSI_BAND1_2_ID = 118,
    EXT_EFUSE_LOCK_RSSI_BAND2_2_ID = 119,
    EXT_EFUSE_LOCK_RSSI_BAND3_2_ID = 120,
    EXT_EFUSE_LOCK_IPV4_MAC_ADDR_01_ID = 121,
    EXT_EFUSE_LOCK_IPV4_MAC_ADDR_02_ID = 122,
    EXT_EFUSE_LOCK_IPV4_MAC_ADDR_03_ID = 123,
    EXT_EFUSE_LOCK_USB_SDIO_PID_ID = 124,
    EXT_EFUSE_LOCK_USB_SDIO1_VID_ID = 124,
    EXT_EFUSE_SLE_EFUSE_ID = 125,
    EXT_EFUSE_ALL_LOCK_ID = 126,
    EXT_EFUSE_CUSTOM_RESERVE_ID = 127,
    EXT_EFUSE_CUSTOM_RESERVE_LOCK_ID = 128,
    EXT_EFUSE_MAX = 129,
    EXT_EFUSE_LOCK_MAX = 129,
} osal_efuse_id;

typedef struct {
    osal_u16 id_start_bit;    /* 起始 bit位 */
    osal_u16 id_size;         /* 以bit为单位 */
} osal_efuse_stru;

osal_u32 uapi_efuse_read(osal_efuse_id id, osal_u8 *data, osal_u8 data_len);
osal_u32 uapi_efuse_write(osal_efuse_id id, osal_u8 *data, osal_u8 data_len);
unsigned int efuse_write_dev_addr(unsigned char *pc_addr, unsigned char addr_len);
unsigned int efuse_write_pid_vid(unsigned short pid, unsigned short vid);
osal_u32 uapi_efuse_get_lockstat(osal_u64 *state);
osal_u32 uapi_efuse_lock(osal_efuse_id lock_id);

#ifdef CONFIG_HCC_SUPPORT_UART
osal_u32 plat_efuse_get_read_data_saved(osal_u8 *data, osal_u16 len);
osal_u32 plat_efuse_get_write_data_saved(osal_u8 *data, osal_u16 len);
osal_u32 efuse_wait_init(osal_void);
osal_void efuse_wait_destroy(osal_void);
#endif

osal_u32 efuse_write_spark_addr(osal_u8 *pc_addr, osal_u8 addr_len);

#ifdef __cplusplus
#if __cplusplus
        }
#endif
#endif

#endif

